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A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology
(Slovak Univ Technology, 2017) Aytar, Oktay; Tangel, Ali; Afacan, Engin
This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/-0.22 LSB of DNL and +0.01/-0.44 LSB of INL, layout area of 0.27 mm(2), and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.
A 10-GSamples/s track and hold amplifier using reference current source unaffected by temperature in 0.18μm SiGe BiCMOS technology
(Ieee, 2018) Talay, Yasin; Aytar, Oktay
This paper presents design and simulation of a track and hold amplifier(THA) and a temperature independent reference current circuit for high speed analog digital converter in 0.18 μm SiGe BiCMOS process BCS180G of HHNEC. The THAs circuit is based on the switched emitter follower topology. Therewithal, the reference current source circuit consists of a proportional to absolute temperature(PTAT) and complementary to absolute temperature(CTAT) circuits. The reference current source unaffected by temperature is working with an accuracy of %0.4 between -45 degrees C and 120 degrees C. Respectively, the power supply voltage of the designed THAs circuits and temperature independent reference current circuit is 5V and 3.3V. The active layout area of designed circuit is 0.02534mm(2)(132 mu m x 192 mu m), consuming 465mW at 10GS/s sampling rate.
4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı
(2019) Talay, Yasin; Aytar, Oktay
Yapılan bu çalışmada, Tanner Tools Pro devre tasarım programında 0.25?m CMOS model kütüphanesikullanılarak flash tabanlı 4 bit Zaman-Sayısal Dönüştürücü(Z /S)(Time-to-Digital Converter(TDC)) yapısıönerilmiştir. Tasarlanan zaman-sayısal dönüştürücü devresi; zaman geciktirme birimi, karşılaştırıcı, dinamiktutucu, çoğullayıcı devre ve PLA-ROM devre bloklarından oluşmaktadır. Önerilen bu Z/S dönüştürücü tasarımı3.3V besleme gerilimi altında toplam 126.3mW güç harcamaktadır. Tasarlanan Z/S dönüştürücünün çözünürlüğü1.31ns olup, INL değeri (-0.28/0.29)LSB ve DNL değeri (-0.2/+0.6) LSB olarak bulunmuştur.
40 GS/s 5 bit time interleaved analog to digital converter in 0.18 mu m SiGe BiCMOS process
(PLEIADES PUBLISHING INC, 2021) Talay, Yasin; Aytar, Oktay
This paper presents the transistor-level schematics, layout design considerations, and post-layout simulation of a four-channel 5 bit 40 GS/s BiCMOS Time-Interleaved Analog to Digital Converter (TI-ADC) by using 0.18 mu m SiGe BiCMOS technology library. This proposed structure has been propounded as a solution for systems that require a high sampling rate for the systems such as wireless and high-speed data communication systems, application of the internet of things and instrumentation and measurement systems, etc. The designed TI-ADC consists of Track and Hold Amplifier (THA) based switch-emitter follower which is not affected by temperature variation, 5 bit Flash ADC and 4 x 1 multiplexer circuit. The supply voltage of the THA circuit and the other circuits in the proposed TI-ADC are 5 and 3.3 V, respectively. For the simulation, the analog input of TI-ADC is selected as a ramp-shaped signal with amplitude in a range of 1.60 to 2.60 V. The post-layout simulation results show that, with a 153.8 MHz analog input and 40 GHz sampling rate, the DNL and INL values are measured -0.21 LSB and 0.26 LSB, -0.2 LSB and 0.35 LSB, respectively. The post-simulations indicate that the effective number of bits (ENOB), active chip area and signal-to-noise ratio (SNR) are 4.37 bits, (0.430 x 0.412) mm(2) and 28.01 dB respectively, with a bandwidth of 50 MHz, a sampling frequency of 40 GHz. The total power consumption of TI-ADC is 2.6 W.
A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder
(Tubitak Scientific & Technical Research Council Turkey, 2013) Aytar, Oktay; Tangel, Ali; Şahin, Kudret
This paper presents a 5-bit flash analog-to-digital converter design using the 0.18-mu m Taiwan Semiconductor Manufacturing Company's CMOS technology library. The designed system consists of 2 main blocks, a comparator array, and a digital decoder. The digital decoder contains a latch, 1-of-N decoder, and fat-tree encoder units. The 1-of-N decoder is implemented using 2 x 1 multiplexers. As a result, the active die area and the power consumption are reduced, in addition to an increase in the sampling frequency. The power supply voltage range for the overall system is +/- 0.9 V. For testing purposes, a ramp signal of between -0.45 V and 0.7 V is applied to the converter input. The sampling frequency is 5 Gs/s. The simulation results include a maximum power consumption of 28 mW, integral nonlinearity values of between -0.65 least significant bits (LSB) and +0.01 LSB, differential nonlinearity values of between -0.3 LSB and +0.13 LSB, and an active die area of 0.1 mm(2).
CMOS inverter tabanlı karşılaştırıcı devrelerinin incelenmesi
(Ieee, 2018) Keleş, Fatmanur; Aytar, Oktay
In this study, the performance of the CMOS inverter circuit with active load, which can be used as a comparator structure in analogue digital converter circuits, is investigated with respect to other CMOS inverter circuits by using 0.25 mu m CMOS technology library in Cadence Virtuoso 6.13 design program. As a result of the analyzes made, it is seen that the proposed structure only consumes 1,041 uW and the delay time is 36.11 ps. The power dissipation, which the proposed design consumes, is significantly lower than the other designed CMOS inverter circuits. Therefore, when the proposed architecture is used in the comparator block of high-speed parallel analogue digital converters, power consumption is likely to decrease.
Comparative analysis of transformer fault classification based on DGA data using machine learning algorithms
(Ieee, 2024) Çoban, Melih; Fidan, Murat; Aytar, Oktay
Dissolved gas analysis (DGA) is considered a leading technique for fault classification in power transformers. However, accurate analysis results can only be achieved if the measured gases are interpreted, appropriately. In DGA interpretation, traditional techniques, artificial intelligence techniques such as machine learning algorithms, and hybrid techniques are generally used. In this study, four well-known machine learning algorithms have been compared in terms of DGA fault classification: Support Vector Machine (SVM), K-Nearest Neighbor (KNN), Naive Bayes (NB) and Decision Tree (DT). The lowest accuracy rate was obtained as 63.63% using the NB algorithm and raw data. In addition to raw data, data converted to logarithmic form has been also used to develop classification models. The highest accuracy rate was determined as 94.54% using the DT algorithm and logarithmic data. The obtained results have been demonstrated the efficiency and stability of the DT algorithm for transformer fault classification, especially when the data was appropriately preprocessed.
Darlington CMOS inverter tabanlı paralel analog-sayısal dönüştürücü tasarımı
(2018) Aytar, Oktay
Yapılan bu çalışmada, CMOS eşik gerilimine göre çalışan Darlington CMOS İnverter devresi kullanılarak 4-bit paralel analog-sayısal dönüştürücü(A/S) yapısı önerilmiştir. Bu yüzden genel blok yapıda kullanılan nicemleme gerilimlerini elde etmek için gerekli olan direnç bölme dizisine ihtiyaç kalmamıştır. Darlington yapısı, genellikle bipolar transistor için kullanılan bir yapı iken burada CMOS yapısı için önerilmiştir. Bu sayede kullanılan inverter devresinin kazancı artırılmıştır. Önerilen 4-bit paralel A/S dönüştürücü için besleme gerilimi +1.8V, sistemin saat frekansı 10GHz, analog giriş işaretinin frekansı 100MHz alındığında elde edilen benzetim sonuçlarına göre güç tüketimi 96.6mW, INL hatası (0/-1.24)LSB, DNL hatası ise (-0.71/+0.82)LSB olarak ölçülmüştür. Tasarımı yapılan sistemin benzetim sonuçları şematik devre üzerinden alınmıştır
Dermoskopik Görüntülerde Lezyon Bölütleme İşlemlerinde K-ortalama Kümeleme Algoritmasının Kullanımı
(2020) Ilkin, Sümeyya; Aytar, Oktay; Gençtürk, Tuğrul Hakan; Şahin, Suhap
Melanom cilt kanserinin erken evrelerinde yapılan teşhisler, iyileşme prognozuna olanetkilerinden dolayı hayati önem taşımaktadır. Yapılan bu teşhisler büyük oranda cildin görseldeğerlendirmesiyle yapılmaktadır. Dolayısıyla, yapılan bu görsel değerlendirme sonucu konulanteşhis çoğunlukla doktorların uzmanlığına bağlı olduğu için, sübjektif bir değerlendirmeolmaktadır. Yapılan bu çalışmada, doktorlar tarafından konulan teşhislerdeki doğruluk oranlarınıartırmak için cilt görüntülerindeki lezyon bölgelerinin bölütleme işlemi K-ortalama kümelemealgoritması ile yapılmaktadır. Algoritmada, K merkezi sayısı 2 ve 4 değerleri seçilerek sistem testedilmektedir. Test aşamasında özel bir melanom veri seti kullanılmıştır. Elde edilen değerlerinanaliz işlemleri, Tepe Sinyali Gürültü Oranı (PSNR) ve Korelasyon Katsayısı (CC) metriklerikullanılarak gerçekleştirilmiştir. Yapılan bu çalışmanın performansı, daha önce tarafımızcagerçeklenen Canny kenar belirleme ve ortalama kayma algoritmaları ile karşılaştırılarakdeğerlendirilmiştir. Yapılan bölütleme işleminde, merkez sayısı 4 seçilen K-ortalama kümelemealgoritmasında en yüksek PSNR değeri 17,1591dB olarak tespit edilmiştir. Metrik sonuçlarincelendiğinde, K-ortalama kümeleme algoritmasında merkez sayısı 4 olarak seçildiğinde eldeedilen sonuçların daha iyi olduğu gözlemlenmiştir.
Design and implementation of drive and control system for ultrasonic motor over power line communication
(Taylor & Francis Inc, 2024) Daldal, Nihat; Aytar, Oktay; Bekiroğlu, Erdal; Bal, Güngör
In this study, remote control application of an ultrasonic motor (USM) has been achieved over the power line communication (PLC) system. Fast, practical, affordable and effective operating mode is essential for the USM. This study aimed to develop an original, efficient, effective and economical method. Drive and control of USM control has been succeeded with the developed PLC control system. A two-phase high-frequency inverter, a power line transmitter, and a power line receiver circuits have been designed to drive and control of the ultrasonic motor. Required measurements are acquired from the power line to select the most suitable communication frequency and coupling circuit impedance for the PLC system. For the communication frequency and impedance value measurements the receiver and the transmitter circuits have been designed. The PLC-controlled system has been tested for different operating conditions of the ultrasonic motor. USM control has been accomplished over the existing power line without using extra cables and interfaces for communication. The obtained results show that the PLC-controlled system is practical, reliable, cost-effective, and feasible for the remote control of the USM. This research contributes a new and essential perspective for the PLC-based remote control studies in addition to the USM drive and control strategies.
Design of a 5-Bit fully parallel analog to digital converter using common gate differrential mos pair-based comparator
(Slovak Univ Technology, 2015) Aytar, Oktay
This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence 105 141 design platform and NCSU(North Carolina State University) design kit with 0.18 mu m CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (-0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.
Effects of device variables to radiofrequency (RF) applications
(Taylor & Francis Inc, 2019) Görgü, Metin; Gökkaya, Ali; Karabekmez, Furkan Erol; Aytar, Oktay; Kızılkan, Jehat; Karanfil, Ertuğrul; Astarcı, Hesna Müzeyyen
RF devices have frequency, power and duration setting options, it is important to make sure that the device meets the targeted values at the head output. This study was made to evaluate the RF device output value accuracy and the effects of different frequencies on the tissue heat levels. RF was applied to invitro tissues obtained from surgical operations, and invivo tissues during operations. Heat differences and depth were measured by laser/IR thermometer and thermal infrared camera. First, the output frequency and power values provided by the device were approved. Then, three three heads (monopolar, bipolar and tripolar) with three different frequencies (1,7, 20 MHz) were used. Depth of heat increase was evaluated in millimeters. The results showed that temperature increase varied between 10 degrees C and 30 degrees C at different depths using different frequencies. Heating of the skin with a radiofrequency device in a therapeutic dose is possible if the appropriate frequency and adequate power values are applied. Because the therapeutic temperature is close to the complication limit, the practitioner should be an expert using the device, well-knowledgeable about the regional skin structure and thickness, as well as be able to properly adjust the application doses in order to get therapeutic results.
The investigation of CMOS inverter based comparator circuits
(Institute of Electrical and Electronics Engineers Inc., 2018) Keleş, Fatmanur; Aytar, Oktay
In this study, the performance of the CMOS inverter circuit with active load, which can be used as a comparator structure in analogue digital converter circuits, is investigated with respect to other CMOS inverter circuits by using 0.25?m CMOS technology library in Cadence Virtuoso 6.13 design program. As a result of the analyzes made, it is seen that the proposed structure only consumes 1,041 uW and the delay time is 36.11 ps. The power dissipation, which the proposed design consumes, is significantly lower than the other designed CMOS inverter circuits. Therefore, when the proposed architecture is used in the comparator block of high-speed parallel analogue digital converters, power consumption is likely to decrease. © 2018 IEEE.
A TIQ based 6-bit 8 Gs/s time interleaved ADC design
(Springer, 2022) Tangel, Ali; Yürekli, Lütfiye Büşra; Aytar, Oktay
This paper presents design of a 6-bit two channel time interleaved (TI) ADC in TSMC 180 nm CMOS technology. Threshold Inverter Quantization (TIQ) based flash ADC cores are used in both TI channels. In this design, speed performance and low power properties are focused design goals. For this purpose, standart CMOS logic gates are preferred as much as possible together with the so-called TIQ comparator structure, which is also a CMOS logic for the analog part of the flash ADC cores. The aspect ratio of the MOS transistors used in the design are choosen carefully to be able to achieve high performance goals as much as possible. The main contribution of this study is to employ the TIQ technique for the second time in TI ADC architectures. The first time realization was also presented by the same authors in ELECO 2018 conference. However, resolution is now increased to 6-bit and more professional design tool is used. Moreover, important design updates became necessary in some of the design blocks. According to simulation results, the proposed TI ADC has the sampling rate of 8 Gs/s. The simulation results also include + 0.148/- 0.574 LSB of INL and + 0.195/- 0.163 LSB of DNL values obtained from DC results. The DNL and INL calculations were also obtained using transient analysis results. While the power consumption of a single flash ADC core at 4 Gs/s is 69.82 mW, the power consumption of the complete two-channel TI ADC is 166.5 mW at 8 Gs/s sampling rate. The fabrication of the proposed ADC is projected as a future work.

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