A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology
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Dosyalar
Tarih
2017
Yazarlar
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Slovak Univ Technology
Erişim Hakkı
info:eu-repo/semantics/openAccess
Özet
This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/-0.22 LSB of DNL and +0.01/-0.44 LSB of INL, layout area of 0.27 mm(2), and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.
Açıklama
Anahtar Kelimeler
Analog-to-Digital Converters, CMOS ADC, Time Interleaved ADC, Flash ADC
Kaynak
Journal Of Electrical Engineering-Elektrotechnicky Casopis
WoS Q Değeri
Q4
Scopus Q Değeri
Q3
Cilt
68
Sayı
6
