The investigation of CMOS inverter based comparator circuits

In this study, the performance of the CMOS inverter circuit with active load, which can be used as a comparator structure in analogue digital converter circuits, is investigated with respect to other CMOS inverter circuits by using 0.25?m CMOS technology library in Cadence Virtuoso 6.13 design program. As a result of the analyzes made, it is seen that the proposed structure only consumes 1,041 uW and the delay time is 36.11 ps. The power dissipation, which the proposed design consumes, is significantly lower than the other designed CMOS inverter circuits. Therefore, when the proposed architecture is used in the comparator block of high-speed parallel analogue digital converters, power consumption is likely to decrease. © 2018 IEEE.