Impact of interfacial layer using ultra-thin SiO2 on electrical and structural characteristics of Gd2O3 MOS capacitor

The aim of present study is to improve the quality of Gd2O3/p-Si MOS structure by reducing interface trap charge density. Therefore, the ultra-thin SiO2 layer was grown to high-k/Si interface. The effect of the post deposition annealing on the structural properties of the Gd2O3/SiO2 films and electrical characteristics of the Al/Gd2O3/SiO2/p-Si/Al were investigated for three different temperature. Besides, the effect of the series resistance and measurement frequency on the electrical characteristics of the p-MOS capacitors was examined in detail. 118 nm-thick Gd2O3 films were grown by RF magnetron sputtering following the 5 nm-thick SiO2 deposition on p type Si wafer by dry oxidation method. While the Gd2O3 monoclinic characteristic peaks were observed in the Gd2O3/SiO2/Si structures annealed at 600 A degrees C and 800 A degrees C, the XRD spectra of as-deposited and annealed at 400 A degrees C sample pointed out Gd silicate formation. -Si, -O, -Gd, and -H bonds were defined in the FTIR spectra of all samples. The frequency dependent capacitance-voltage (C-V) and conductance-voltage (G/omega-V) characteristics of Gd2O3/SiO2 MOS capacitor were measured. Strong accumulation capacitance values in these devices did not change significantly depending on frequency. Unlike from the MOS capacitor with as-deposited and annealed Gd2O3/SiO2 at 400 A degrees C, the interface trap charge density increased with increasing voltage frequency for the samples annealed at 600 A degrees C and 800 A degrees C. No significant change in the border trap density with increasing frequency was observed in the MOS capacitor except for as-deposited device. The barrier height increased with increasing frequency for all Gd2O3/SiO2 MOS capacitors.