40 GS/s 5 bit time interleaved analog to digital converter in 0.18 mu m SiGe BiCMOS process

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dc.authorid0000-0001-7664-103Xen_US
dc.contributor.authorTalay, Yasin
dc.contributor.authorAytar, Oktay
dc.date.accessioned2023-05-30T07:24:42Z
dc.date.available2023-05-30T07:24:42Z
dc.date.issued2021en_US
dc.departmentBAİBÜ, Mühendislik Fakültesi, Elektrik Elektronik Mühendisliği Bölümüen_US
dc.description.abstractThis paper presents the transistor-level schematics, layout design considerations, and post-layout simulation of a four-channel 5 bit 40 GS/s BiCMOS Time-Interleaved Analog to Digital Converter (TI-ADC) by using 0.18 mu m SiGe BiCMOS technology library. This proposed structure has been propounded as a solution for systems that require a high sampling rate for the systems such as wireless and high-speed data communication systems, application of the internet of things and instrumentation and measurement systems, etc. The designed TI-ADC consists of Track and Hold Amplifier (THA) based switch-emitter follower which is not affected by temperature variation, 5 bit Flash ADC and 4 x 1 multiplexer circuit. The supply voltage of the THA circuit and the other circuits in the proposed TI-ADC are 5 and 3.3 V, respectively. For the simulation, the analog input of TI-ADC is selected as a ramp-shaped signal with amplitude in a range of 1.60 to 2.60 V. The post-layout simulation results show that, with a 153.8 MHz analog input and 40 GHz sampling rate, the DNL and INL values are measured -0.21 LSB and 0.26 LSB, -0.2 LSB and 0.35 LSB, respectively. The post-simulations indicate that the effective number of bits (ENOB), active chip area and signal-to-noise ratio (SNR) are 4.37 bits, (0.430 x 0.412) mm(2) and 28.01 dB respectively, with a bandwidth of 50 MHz, a sampling frequency of 40 GHz. The total power consumption of TI-ADC is 2.6 W.en_US
dc.identifier.citationYasin Talay, Oktay Aytar 40 GS/s 5 bit Time Interleaved Analog to Digital Converter in 0.18 µm SiGe BiCMOS Process. J. Commun. Technol. Electron. 66 (Suppl 2), S201–S212 (2021). https://doi.org/10.1134/S1064226921140199en_US
dc.identifier.doi10.1134/S1064226921140199
dc.identifier.endpageS212en_US
dc.identifier.issn1064-2269
dc.identifier.issn1555-6557
dc.identifier.issueSUPPL 2en_US
dc.identifier.scopus2-s2.0-85128477400en_US
dc.identifier.scopusqualityQ3en_US
dc.identifier.startpageS201en_US
dc.identifier.urihttp://dx.doi.org/10.1134/S1064226921140199
dc.identifier.urihttps://hdl.handle.net/20.500.12491/10995
dc.identifier.volume66en_US
dc.identifier.wosWOS:000779481600015en_US
dc.identifier.wosqualityQ4en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.institutionauthorAytar, Oktay
dc.language.isoenen_US
dc.publisherPLEIADES PUBLISHING INCen_US
dc.relation.ispartofJournal of Communications Technology and Electronicsen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectAnalog-Digital Conversionen_US
dc.subjectTime Interleaved Analog-To-Digital Converteren_US
dc.subjectTrack And Hold Amplifieren_US
dc.subjectLow-Poweren_US
dc.subjectAdcen_US
dc.subjectDesignen_US
dc.title40 GS/s 5 bit time interleaved analog to digital converter in 0.18 mu m SiGe BiCMOS processen_US
dc.typeArticleen_US

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