A TIQ based 6-bit 8 Gs/s time interleaved ADC design

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dc.authorid0000-0002-0569-6399en_US
dc.authorid0000-0001-7664-103Xen_US
dc.authorid0000-0002-1794-314Xen_US
dc.contributor.authorTangel, Ali
dc.contributor.authorYürekli, Lütfiye Büşra
dc.contributor.authorAytar, Oktay
dc.date.accessioned2023-09-05T09:05:00Z
dc.date.available2023-09-05T09:05:00Z
dc.date.issued2022en_US
dc.departmentBAİBÜ, Mühendislik Fakültesi, Elektrik Elektronik Mühendisliği Bölümüen_US
dc.descriptionKocaeli University Scientific Research Projects Coordination Unit(Kocaeli University)en_US
dc.description.abstractThis paper presents design of a 6-bit two channel time interleaved (TI) ADC in TSMC 180 nm CMOS technology. Threshold Inverter Quantization (TIQ) based flash ADC cores are used in both TI channels. In this design, speed performance and low power properties are focused design goals. For this purpose, standart CMOS logic gates are preferred as much as possible together with the so-called TIQ comparator structure, which is also a CMOS logic for the analog part of the flash ADC cores. The aspect ratio of the MOS transistors used in the design are choosen carefully to be able to achieve high performance goals as much as possible. The main contribution of this study is to employ the TIQ technique for the second time in TI ADC architectures. The first time realization was also presented by the same authors in ELECO 2018 conference. However, resolution is now increased to 6-bit and more professional design tool is used. Moreover, important design updates became necessary in some of the design blocks. According to simulation results, the proposed TI ADC has the sampling rate of 8 Gs/s. The simulation results also include + 0.148/- 0.574 LSB of INL and + 0.195/- 0.163 LSB of DNL values obtained from DC results. The DNL and INL calculations were also obtained using transient analysis results. While the power consumption of a single flash ADC core at 4 Gs/s is 69.82 mW, the power consumption of the complete two-channel TI ADC is 166.5 mW at 8 Gs/s sampling rate. The fabrication of the proposed ADC is projected as a future work.en_US
dc.description.sponsorshipKocaeli University Scientific Research Projects Coordination Unit [BAP FBA-2020-2057]en_US
dc.identifier.citationTangel, A., Yurekli, L. B., & Aytar, O. (2022). A TIQ based 6-bit 8 Gs/s time interleaved ADC design. Analog Integrated Circuits and Signal Processing, 113(2), 211-221.en_US
dc.identifier.doi10.1007/s10470-022-02083-2
dc.identifier.endpage221en_US
dc.identifier.isbn0925-1030
dc.identifier.issn1573-1979
dc.identifier.issue2en_US
dc.identifier.scopus2-s2.0-85137217061en_US
dc.identifier.scopusqualityQ3en_US
dc.identifier.startpage211en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s10470-022-02083-2
dc.identifier.urihttps://hdl.handle.net/20.500.12491/11659
dc.identifier.volume113en_US
dc.identifier.wosWOS:000847248000001en_US
dc.identifier.wosqualityQ4en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.institutionauthorAytar, Oktay
dc.language.isoenen_US
dc.publisherSpringeren_US
dc.relation.ispartofAnalog Integrated Circuits and Signal Processingen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectTIQ Comparatoren_US
dc.subjectFlash ADCen_US
dc.subjectTime Interleaveden_US
dc.subjectAnalog-Digital Converteren_US
dc.subjectDigital Calibrationen_US
dc.subjectCmosen_US
dc.titleA TIQ based 6-bit 8 Gs/s time interleaved ADC designen_US
dc.typeArticleen_US

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