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    A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology
    (Slovak Univ Technology, 2017) Aytar, Oktay; Tangel, Ali; Afacan, Engin
    This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/-0.22 LSB of DNL and +0.01/-0.44 LSB of INL, layout area of 0.27 mm(2), and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.
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    A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder
    (Tubitak Scientific & Technical Research Council Turkey, 2013) Aytar, Oktay; Tangel, Ali; Şahin, Kudret
    This paper presents a 5-bit flash analog-to-digital converter design using the 0.18-mu m Taiwan Semiconductor Manufacturing Company's CMOS technology library. The designed system consists of 2 main blocks, a comparator array, and a digital decoder. The digital decoder contains a latch, 1-of-N decoder, and fat-tree encoder units. The 1-of-N decoder is implemented using 2 x 1 multiplexers. As a result, the active die area and the power consumption are reduced, in addition to an increase in the sampling frequency. The power supply voltage range for the overall system is +/- 0.9 V. For testing purposes, a ramp signal of between -0.45 V and 0.7 V is applied to the converter input. The sampling frequency is 5 Gs/s. The simulation results include a maximum power consumption of 28 mW, integral nonlinearity values of between -0.65 least significant bits (LSB) and +0.01 LSB, differential nonlinearity values of between -0.3 LSB and +0.13 LSB, and an active die area of 0.1 mm(2).
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    A TIQ based 6-bit 8 Gs/s time interleaved ADC design
    (Springer, 2022) Tangel, Ali; Yürekli, Lütfiye Büşra; Aytar, Oktay
    This paper presents design of a 6-bit two channel time interleaved (TI) ADC in TSMC 180 nm CMOS technology. Threshold Inverter Quantization (TIQ) based flash ADC cores are used in both TI channels. In this design, speed performance and low power properties are focused design goals. For this purpose, standart CMOS logic gates are preferred as much as possible together with the so-called TIQ comparator structure, which is also a CMOS logic for the analog part of the flash ADC cores. The aspect ratio of the MOS transistors used in the design are choosen carefully to be able to achieve high performance goals as much as possible. The main contribution of this study is to employ the TIQ technique for the second time in TI ADC architectures. The first time realization was also presented by the same authors in ELECO 2018 conference. However, resolution is now increased to 6-bit and more professional design tool is used. Moreover, important design updates became necessary in some of the design blocks. According to simulation results, the proposed TI ADC has the sampling rate of 8 Gs/s. The simulation results also include + 0.148/- 0.574 LSB of INL and + 0.195/- 0.163 LSB of DNL values obtained from DC results. The DNL and INL calculations were also obtained using transient analysis results. While the power consumption of a single flash ADC core at 4 Gs/s is 69.82 mW, the power consumption of the complete two-channel TI ADC is 166.5 mW at 8 Gs/s sampling rate. The fabrication of the proposed ADC is projected as a future work.