Yazar "Asensi, Ignacio" seçeneğine göre listele

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    Latest developments and characterisation results of the MALTA sensors in TowerJazz 180nm for the High Luminosity LHC
    (SISSA Medialab Srl, 2021) Sharma, Abhishek; Allport, Phil; Asensi, Ignacio; Berdalovic, Ivan; Bortoletto, Daniela; Oyulmaz, Kaan Yüksel; Suligoj, Tomislav
    The MALTA sensors are Depleted Monolithic Active Pixel Sensors (DMAPS) made using 180nm TowerJazz CMOS technology. These have been iteratively designed towards achieving a high radiation tolerance for applications such as in the outer layers of the HL-LHC's ATLAS Inner Tracker. To date several design enhancements have been implemented to attain a high time resolution (<2ns), granularity as well as achieving excellent charge collection efficiency uniformly across the pixel geometries. This technology promises to drastically cut the production cost of silicon sensors due to their monolithic design, bypassing the costly stage of bump bonding in hybrid sensors. This talk will provide a detailed overview of the comprehensive characterisation studies conducted on the MALTA and Mini-MALTA sensors as well as present newer functionalities being introduced in the latest iteration, the MALTA2. © Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND 4.0)
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    MALTA3: Concepts for a new radiation tolerant sensor in the TowerJazz 180 nm technology
    (Elseiver, 2022) Dobrijević, Dominik; Allport, Phil; Asensi, Ignacio; Berlea, Dumitru-Vlad; Bortoletto, Daniela; Denizli, Haluk; Oyulmaz, Kaan Yüksel
    The upgrade of the MALTA DMAPS designed in Tower 180 nm CMOS Imaging process will implement the numerous modifications, as well as front-end changes in order to boost the charge collection efficiency after the targeted fluence of 1x10(15) 1 MeVn(eq)/cm(2). The effectiveness of these changes have been demonstrated in recent measurements with a small-scale Mini-MALTA demonstrator chip. Multiple changes in the digital periphery are proposed: The asynchronous address generator will be revised to provide more control over the pulse length. The Synchronization memory will be upgraded with the goal of achieving a sub-nanosecond timing resolution. Serial chip to chip data transfer will be prototyped, in order to gauge the plausibility of implementation on a future full sized chip. Apart from these changes, research of the overall sensor architecture will be discussed as well.